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confidential oc-48/stm-16 framer with vc - posic2gvc? cy7c9536b cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02078 rev. *g revised april 25, 2005 features ? oc-48/sts-48/stm-16, oc-12/sts-12/stm-4, oc-3/sts3/stm-1 rates, concatenated and non-concat- enated ? complies with itu-standards g.707/y.1322 and g.783 [1,2] ? complies with bellcore gr253 rev.1, 1997 [3] ? channelized operation: supports 16xoc-3 and 4xoc-12 within oc-48 stream ? supports tug3 mapping in sdh mode ? virtual concatenation enables secure and dedicated bandwidth provisioning [4] ? up to 16 channels ? from 50-mbps to 1.2-gbps bandwidth per channel ? sts-1 and sts-3c granularity ? full duplex mapping of atm cells over sonet/sdh ? complies with itu-standards i 432.2 [5,6,7] ? full duplex mapping of packet-over-sonet/sdh: ietf rfc 1619/1662/2615 (hdlc/ppp) [8,9,10] ? generic framing procedure (gfp) per ansi t1x1.5 [11,12,13] protocol encapsulator/decapsulator delineates gfp frames with length-crc frame construct ? gfp 268r1 ? user-programmable encapsulation ? user-programmable clear channel transport ? user-programmable sonet/sdh bypass ? programmable frame tagging engine for packet preclassification enables such features as ? mpls label lookup and tagging ? ppp: lcp and ncp tagging ? ppp control packets optional ly sent to host cpu interface ? mac/layer 3 address look up and tagging. ? programmable a1a2 processing bypass in rx direction with frame sync input ? complete section overhead (soh), line overhead (loh), and path over head (poh) processing ? aps extraction, cpu interrupt generation, and programmable insertion of aps byte ? line side aps port interface ? provision for protection switching on sonet/sdh port ? programmable prbs generator and receiver ? serial port to access line/section data communication channel (dcc) and voice communication channel (vcc) ? full duplex oif-spi (pos-phy)/utopia level 3 interface [14,15] ? 16-bit/32-bit host cpu interface bus ? jtag and boundary scan ? glueless interface with cypress cys25g0101dx oc-48 phy ? 0.18-um cmos, 504-pin bga package ? +1.8v for core, +3.3v for lvttl i/o, +1.5v/+3.3v for hstl/lvpecl i/o supply, and +0.75v/2.0v reference applications ? multi-service nodes ? atm switches and routers ? packet routers and multiservice routers ? sonet/sdh/add-drop mux for packet/data applications ? sonet/sdh/atm/pos test equipment notes: 1. itu-t recommendation g.707. ?network node interface for the synchronous digital hierarchy.? 1996. 2. itu-t recommendation g.783. ?characterist ics of synchronous digital hierarchy (s dh) equipment functional blocks.? 2000. 3. bellcore publication gr-253-core. ?synchronous optical network (sonet) transport systems: common generic criteria.? 1997. 4. jones, n., lucent microelectronics, and c. murton, nortel ne tworks. ?extending ppp over sonet/dsh with virtual concatenation, high-order and low-order payloads.? internet draft. june 2000. 5. itu-t recommendation i.432.3. ?b-isdn user-n etwork interface?physical layer specification: 1544 kbit/s and 2048 kbit/s operat ion.? 1999. 6. american national standards institute. ?synchronous optical network (sonet)?basic description including multiplex structure, rates and formats.? ansi t1.105-1995. 7. american national standards institute. ?synchronous optical network (sonet)?payload mappings.? ansi t1.105.02?1998. 8. simpson, w. ?ppp over sonet/sdh.? rfc 1619. may 1994. 9. simpson, w., ed. ?ppp in hdlc-like framing,? rfc 1662. daydreamer . july 1994. 10. malis, a. and w. simpson. ?ppp over sonet/sdh,? rfc 2615. june 1999. 11. hernandez-valencia, e., lucent technologies. ?a generic frame format for data over sonet (dos).? march 2000. 12. gorshe, c. and steven. t1x1.5/99-204, t1 105.02. draft text for mapping ieee 802.3 ethernet mac frames to sonet payload. jul y 1999. 13. hernandez-valencia, e., lucent technologies. t1x1.5/2000-209. ?generic framing procedure (gfp) specification.? october 9?13, 2000. 14. atm forum, technical committee. uutopia 3 physical layer interface.? af-phy-0136.000. november 1999. 15. can, r. and r. tuck. ?system packet interface level 3 (spi-3): oc-48 system interface for phys ical and link-layer devices.? oif-spi3-01.0. june 2000.
confidential cy7c9536b document #: 38-02078 rev. *g page 2 of 46 link layer device for ethernet, fc, dvb, atm, etc. spi - 3 hbst utopia oc-48 cys25g0101dx transceiver o/e e/o posic device nobl sram cpu lan, cbr, client ports, etc. figure 1. posic2gvc system application diagram receiv e sone t overhe ad insertio n cpu interface cpuclk cputs_n/ capuads_n cpusel cpublast_n cputa_n chipsel cpuint cpuclkfail cpuwrrd cpuad[31:0] mode programmable frame tagging receive utopia/spi-3 interface rval renb rfclk rdat[31:0] radd[7:0] rmod[1:0] rprty rerr reor rsop rca rsx text tx sonet line interface transmit sonet framer pointer processor sonet framing bypass transmit sonet overhead processor jtag interface tck trst tdi tms tdo general pins rst_n sysclk rstout_n clkout test[2:0] posic_oen scan_ena transmit utopia/spi-3 interface tfclk terr tdat[31:0] tprty tadd[3:0] tmod[1:0] tsop teop stpa ptca tenb tsx dtca[3:0] receive sonet de-framer sonet framing bypass receive sonet overhead processor rx sonet line interface pointer processor clk16mhz clk2mhz pohsdout rpohstart tpohstart re1strobe re2strobe tohsdour te1strobe te2strobe tohsdin pohsdin vc tx (virtual concatenation) tx atm encapsulator tx hdlc tx generic framing procedure (gfp) encapsulator encapsulator vc rx (virtual concatenation) rx atm rx hdlc rx generic framing procedure (gfp) decapsulator decapsulator decapsulator rxd[31:0] rxclk rxframe_pulse lfi rxclks sonetrx_parin txd[31:0] txclki txclkout txframe_pulse sonettx_parout posic2gvc logic block diagram
confidential cy7c9536b document #: 38-02078 rev. *g page 3 of 46 overview the cy7c9536b (posic2gvc ? ) is a highly integrated sonet/sdh framer device for transport of atm and ip packets over sonet/sdh links. it features special functions and architecture to support ne xt-generation optical networking protocols for both sonet/s dh and direct data-over-fiber networks. oif-spi (pos-phy) level 3, utopia level 3 and high-bandwidth synchronous tran sfer (hbst) interfaces are provided on the system side. posic2gvc performs complete soh, loh, and poh processing. complete access to all overhead bytes is provided through register access via th e host cpu interface. access to selected overhead bytes are also available through serial port. optional frame sync input and transport overhead (toh) bypass enables better interface with sts-1 switched streams. the virtual concatenation feature, with up to 16 channels, enables provisioning of se cure, dedicated and right-sized bandwidth for ethernet or atm transport. up to 16 virtual channels can be created with sts-1 or sts-3c granularity. bandwidth from 50 mbps to 1.2 gbps can be allocated per channel. posic2gvc supports packet over sonet/sdh as ppp in hdlc-like frame as per ie tf rfc 1619/1662/2615 (ppp). posic2gvc also supports full duplex atm over sonet/sdh transport in compliance with itu i432.2. posic2gvc supports the new generation generic framing procedure (gfp) protocol encapsulation/decapsulation over sonet/sdh. this protocol engi ne features wire rate framing, frame delineation and deframing with length-crc pair header construct. optional payload scrambling/descrambling and payload fcs are also provided. clear channel mode enables transport of any raw byte streams on selected virtual channels, while the rest of the channels are transporting data through any one of encapsu- lation/decapsulation engines. the programmable frame tagging engine enables wire rate tagging of packets/frames. for new generation networking features such as mpls, this engine can be programmed to tag based on existence/lack of spec ific label/field values, in the first 64 bytes of each packet. this way, packets are tagged for a variety of conditions, all prog rammable by the user, enabling sorting of packets in the incoming data stream and buffering packets accordingly. in a ppp a pplication, cont rol packets can optionally be sent over the host cpu interface directly. sonet/sdh bypass mode allows use of this device for data transport in non sonet/sdh poi nt-to-point and mesh optical networks. transmit in the transmit direction, pack ets are received from the system side, encapsulated/framed and mapped into the sonet/sdh payload. finally the toh is added and sonet/sdh frames are passed onto the fiber side/line side interface on a parallel bus. the system side inte rface can be programmed either as oif-spi level 3, or utopia level 3 or hbst modes. in the utopia mode, atm cells can be received either in 54- (8-bit interface) or 56- (8-bit and 32-b it interfaces) bytes format. the sixth byte carries the channel number of the cell. in case of packets, the interface can be pr ogrammed as oif-spi level 3 or hbst operations. in these cases, the first data transfer always carry the channel number. posic2gvc supports three ba sic types of encapsulation, namely (i) atm, (ii) hdlc frame, and (iii) gfp (frames with length-crc pair header construct based delineation). clear channel or transparent mode (no encapsulation) is also supported. while in operation, only one type of encapsulation can be enabled for all vc channels. some or all of the vc channels can be programmed as clear channels. for clear channels, the encapsulator engine will bypass the encapsu- lation and pass the packets without any processing to the next block. encapsulated packets are transferred to the virtual concate- nation (vc) block along with the channel number. the vc block rearranges the packet/frame flow to support the bandwidth allocation for virtual channels. bandwidth is assigned by allocating a prog rammed number of spes to each channel. the vc block keeps track of the spe under construction by the sonet/s dh framer block and transfers the packets meant for a given channel to the sonet framer. since posic2gvc does not have a packet storage memory on-chip, a channel bandwidth balanced packet flow is expected from the system side. to enable such a balanced transfer, posic2gvc has internal fifo of 512 bytes per channel. the status of fifo is pr ovided through pins to the link layer. finally, the sonet/sdh framer inserts the packet /cells into the sonet/sdh frame. all overhead bytes are added. all alarm bits and status bits are inserted based on the status of incoming frames as well as programming done by the host cpu. the scrambler meets relevant standards and can optionally be disabled. frames are finally sent out on the fiber side interface. if programmed to do so, the sonet/sdh framer can be bypassed and encapsulated packets/frames can be sent directly to the fiber-side interface. receive in the receive direction, sonet/sdh frames are received from the fiber side. data packets/frames are extracted from the payload and passed onto the selected decapsulator engine after compensation for differential delay, in case of virtual concatenation. if the sonet/s dh framer is bypassed, the incoming data stream is directly passed over to the decapsu- lator engine. data packets/frames are then decapsulated and sent to the programmable frame tagging engine. they are then analyzed and tagged before sent out to the system side via the oif-spi level 3, utopia or hbst interface. tagging of frames is optional. sonet/sdh frames entering from the fiber side are synchro- nized and the frame boundary is identified with a1a2 bytes. frames can be optionally synchronized with frame_sync_input to identify the boundary. descrambling is performed to retrieve scrambled frames. complete processing of all overhead bytes, section, line and path, is performed and all alarm bits are verified and alarms are raised as programmed. full access to all overhead bytes is provided through register access. access to selected overhead bytes is also provided through serial bus. the sonet/sdh deframing can be entirely bypassed. the extracted payload is transferred to the vc block where it is reorganized to compensate for any differential delay encountered in the network from the virtual concatenation
confidential cy7c9536b document #: 38-02078 rev. *g page 4 of 46 channel. for this purpose, up to 256 frames are stored in external memory. the vc block then passes the payload stream to the selected decapsulator engine. the selected decapsulator engine delineates the payload stream, decapsulates and extracts packets/cells from the stream. descrambling of packets/cells is optional. the packets/cells are then sent out to the programmable frame tagging engine. the frame tagging engine optionally tags the packet/cell as programmed. the packet/cell is then transferred to the link layer device, through the syst em interface (oif-spi/utopia level 3, or hbst), with an additional eight bits of information. four bits specify the vc channel and the other four bits specify the tag. virtual concatenation virtual concatenation creates multiple virtual payloads of different sizes within the incoming sonet/sdh frame, effec- tively creating multiple channels of different bandwidth. the advantages of vc are: ? efficient and dedicated bandwidth allocation. ? compatibility with tdm acce ss infrastructure. virtually concatenated channels can coexist with aware and nonaware network elements on the same shared access. ? independence from upper layer data protocol/frame format. ? fine granularity channels are extensible and easily provi- sionable. posic2gvc supports vc for all types of packets/frames/ protocols it transports on sonet/sdh. up to 16 channels can be created using sts1/vc-3, sts3c/vc-4, sts12c/vc4-4c and sts24c/vc4-8c. posic2gvc also supports non-virtually concatenated channels such as sts3c and sts12c. ta ble 1 shows a list of virtually concatenated channel bandwidth supported by posic2gvc. virtual concatenation requires specific overhead processing capabilities only at the path terminating equipment. it remains transparent at the intermediate nodes in the network. it is possible therefore that two or more different spes, virtually bonded to create a channel, travel through different routes in the network. hence, they can a rrive at the destination in the order different from t he order at the point of origination. delay encountered in arrival of two virtually concatenated spes in a frame is called differential delay. to compensate for differential delay, the spe received earlier need to be stored until the particular spe, which is previous in the order but faces longer travel time, arrives at the te rminating node. posic2gvc can store up to 256 sonet/sdh frames in external memory, which can compensate for 16 ms of differential delay. for differential delay higher th an that, posic2 gvc raises an alarm. notes: 16. all vc mode channel configurations require a sysclk frequency of 133.33 mhz. 17. please refer to device manual for allowed combinati ons of virtual channels using stsx-1v/vcx-1v granularity. table 1. virtual concatenated channel bandwidth [16] vc-3-1v/sts-1-1v [17] (~50 mbps) vc-3-2v/sts-1-2v (~100 mbps) vc-3-3v/sts-1-3v (~150 mbps) vc-3-4v/sts-1-4v (~200 mbps) vc-3-5v/sts-1-5v (~250 mbps) vc-3-6v/sts-1-6v (~300 mbps) vc-3-7v/sts-1-7v (~350 mbps) vc-3-8v/sts-1-8v (~400 mbps) vc-4-1v/sts-3c-1v [17] (~150 mbps) vc-4-2v/sts-3c-2v (~300 mbps) vc-4-3v/sts-3c-3v (~450 mbps) vc-4-4v/sts-3c-4v (~600 mbps) vc-4-5v/sts-3c-5v (~750 mbps) vc-4-6v/sts-3c-6v (~900 mbps) vc-4-7v/sts-3c-7v (~1.05 gbps) vc-4-8v/sts-3c-8v (~1.2 gbps) vc-4-4c-1v/sts-12c-1v [17] (~600 mbps) vc-4-4c-2v/sts-12c-2v (~1.2 gbps) vc4-8c-1v/sts-24c-1v [17] (~1.2gbps)
confidential cy7c9536b document #: 38-02078 rev. *g page 5 of 46 generic frame encapsulation/decapsulation posic2gvc supports a variety of protocols/packets/frames to transport over a sonet/sdh link. for clarity of reference, in this document, framing of pa ckets/cells into these protocols is called ?encapsulation,? and the engine performing encapsu- lation is called an ?encapsulator.? similarly, deframing is called ?decapsulation,? and the engine performing decapsulation is called a ?decapsulator.? three different encapsulator and decapsulator engines are integrated into posic2gvc. the atm encapsulator comput es and adds the hec field, scrambles the cells and passes on to the vc block. in case of underflow, atm encapsulator also creates programmable idle cells. the atm decapsulator checks for hec and integrity of the cell. it descrambles the cells, isolates and discards idle cells and passes atm cells to the programmable frame tagging engine. hdlc encapsulator performs asynchronous control character mapping (accm), stuffing, flag sequence insertion and scrambling. optionally, up to 16 bytes of header is inserted ahead of the packet while framing the packet. the host cpu can program this 16-byte header through register programing. such programmable header insertion enables encapsulation of ppp, frame relay or other protocol. the hdlc decapsulator descrambles the incoming byte stream and searches the flag sequence. upon finding the boundary, decapsulator performs destuffing and accm demapping before passing the packets to the programmable frame tagging engine. the generic framing procedur e (gfp) encapsulator/decap- sulator supports delineation based on length-crc pair header construct. in the transmit direct ion, it computes a 16-bit header crc based on 2-byte length value received from the link layer device. the length and crc fields are inserted as header of the frame ahead of the packet. scrambling of the payload and 32-bit payload crc computation and insertion are optional. figure 2. explanation of virtual concatenation p o s i c sonet cloud p o s i c sonet cloud ch 3 ch 2 15 2 n 16 3 1 ch 1 (oc3 spes may arrive in different order. at receiveing end, posic stores the spes in external memory to re-arrange them in correct order.) link layer ch 1 1gb packet (gigabit ethernet) ch 2 1gb packet (gigabit ethernet) ch 3 (3x100 mb ethernet or tdm in clear channel mode) 300mb link layer ch 1 1gb packet ch 2 1gb packet (gigabit ethernet) ch 3 (3x100 mb ethernet or tdm in clear channel mode) 300mb spi - 3 spi - 3 16 15 n 3 2 1 ch 1 ch 2 ch 3
confidential cy7c9536b document #: 38-02078 rev. *g page 6 of 46 in the receive direction, gfp frames are delineated based on the length-crc construct pair header, integrity verified, payload extracted, optionally descrambled and sent to the programmable frame tagging engine. any selected vc channel can be programmed to become a ?clear channel?. the encapsulator and decapsulator remain in transparent mode for the clear channel and data passes through without any modification. this feature can be used to transport any raw data streams on a portion of bandwidth while the rest of the bandwidth is utilized for protocol traffic. programmable frame tagging engine the programmable frame tagging engine provides preclas- sification of the packets/frames at the wire rate. this helps in utilizing the link layer device more efficiently. the programmable frame tagging engine enables the user to perform preclassification of all the incoming packets into one of the 16 possible categories. since each channel can have up to 16 different categories, and up to 16 virtual concat- enated channels are possible, this engine supports up to 256 different categories. for cla ssification, two-pass comparison can be specified. for each comparison a field of up to six bytes can be selected within the first 64 bytes of the packet and compared with up to 16 programmed values. the comparison is on a bit by bit basis and any bit comparison can be masked with a user programmable mask register. a four-bit tag is attached to the cell/packet, based on the match. host cpu can program these parameters through register programming. the following drawing demonstrates one possible combi- nation of classification with the help of the programmable frame tagging engine. the following functions can be achieved with the help of the programmable frame tagging engine: ? incoming packet analysis to parse packets/frames/cells at wire speed. ? user-programmable routing of control packets to cpu for processing. ? incoming frames tagged based on bits (such as congestion) in incoming packets. ? user-programmable offset to locate ethernet and other frames within dos and other proprietary man networking protocols to allow mpls processing. sonet/sdh bypass posic2gvc supports the so net/sdh framer/deframer bypass mode. host cpu can pr ogram such bypass. in this mode, the data frames/packets, encapsulated by one of the encapsulators, will be transm itted transparently through vc and sonet/sdh blocks to the fiber side and vice versa. system interface the system interface is progra mmable. for application in an atm system, posic2gvc system interface can be programmed to be phy side interface as per utopia level 3 specifications. for variable length packets, posic2gvc system interface can be programmed to be oif-spi level 3. atm cells can also be transferred over oif-spi level 3 bus. system interface can be programmed in hbst mode. in this case, a separate set of address pins are supported on the system side. this mode supports high-speed burst access. protocol/frame types frame tagger spi-3/ utopia spi-3/ utopia virtual concatenation sonet/ sdh framer sonet/ sdh deframer virtual concatenation "clear channel transport" 1) only one framer/deframer active 2) selected vc channels can be declared "clear channel transport" "clear channel transport" atm framer atm deframer hdlc framer hdlc deframer gfp protocol framer gfp protocol deframer figure 3. protocol framers
confidential cy7c9536b document #: 38-02078 rev. *g page 7 of 46 cpu interface posic2gvc can interface with 16-bit or 32-bit cpu. the cpu interface can be pin configured to be compatible with motorola or intel bus interface. the cp u interface provides access to all registers of posic2gvc, coll ates all interrupt generated by various blocks and also supports control packet transfers. line interface the line interface/fiber side interf ace is configurable as 8 bit, 16-bit or 32-bit depending on the clock frequency and data rate. the options shown in ta ble 2 are available. clock source the transmit clock can be programmed to be one of the following sources: ? received clock supplied by the phy ? external transmit clock source. sonet/sdh control packets spi-3 interface rx processing data packets packets not belonging to this node ttl-expired and other discard packets tagging enables sorting of packets by host system errored packets (crc and parity) node-sourced packets to be sinked posic host system data tag #0 tag #1 tag #2 tag #13 data data data tag #14 data data tag #15 tag #n data ........ system memory at figure 4. frame tagging engine data sorting diagram table 2. configuration options bus width clock frequency line rate 8 bits 19.44 mhz oc-3/stm-1 8 bits 77.76 mhz oc-12/stm-4 16 bits 38.88 mhz oc-12/stm-4 16 bits 155.52 mhz oc-48/stm-16 32 bits 77.76 mhz oc-48/stm-16
confidential cy7c9536b document #: 38-02078 rev. *g page 8 of 46 aps port posic2gvc provides a 16-bit aps port for 1+1 protection. the support of a main and standby phy interface connectivity allows several different aps implementation options using posic2gvc. multi-framer aps implementation two posic2gvc devices can be connected to two different transceivers, optics and fibers. posic2gvc enables protection switching with only one device being main and connected to link layer. the standby posic2gvc device is connected to the main posic2gvc device and it is controlled by host cpu. posic2gvc provides aps byte information to the host cpu. the host cpu is expected to take a protection switching decision and provide necessary instructions to both posic2gvc devices. in case of protection switching, in the transmit direction, the main posic2gvc will perform all other operations as programmed, except some of the line and section processing of sonet/sdh framing. t he main posic2gvc device will then pass on the spes to the standby device through the aps port. the standby device will then perform the rest of the line and section processing and transport sonet/sdh frames over standby fiber. similarly, in case of protection switched mode, on the receive side, the standby device will process some of the line and section overhead and transfer the frames to main device through the aps port. the main device will perform the rest of the processing in the receive side. single framer aps implementation a main and slave phy device can be interfaced directly to the main and aps ports of a single posic2gvc device. in this case, the main phy is connected to the main line interface and the standby phy is connected to the aps port. in the posic2gvc transmit path, sonet/sdh data is bridged across the main and aps ports (per linear 1+1 aps requirements). when protection switching, posic2gvc can be programmed to switch line inputs from the main receive port to the aps receive port, or vice versa. this aps scheme provides sole ly optical/phy link level protection. phy standby link layer device posic main phy main posic standby rxs rxs rxs rxm rxm rxm txs txs txs txm txm working channel protection figure 5. posic2gvc aps implementation using two posic devices
confidential cy7c9536b document #: 38-02078 rev. *g page 9 of 46 figure 6. posic2gvc aps implementation using a single posic device txclki txclko txd [15:0] rxd[15:0] rxclk txclko txd[15:0] txclki rxclk rxd[15:0] main oc-48 phy refclk osc sff optical module txclki txclko txd [15:0] rxd[15:0] rxclk txd[31:16] rxclks rxd[31:16] standby phy refclk sff optical module posic2gvc lfi lfi lfi m m
confidential cy7c9536b document #: 38-02078 rev. *g page 10 of 46 pin configuration posic tm (cy7c9536) pin diagram bottom view cy7c9536b (posic2gvc) bottom view
confidential cy7c9536b document #: 38-02078 rev. *g page 11 of 46 pin description signal name i/o pad type pins jtag pin description line interface signals rxframe_pulse i hstl/lvttl /lvpecl 1n optional frame pulse input for line interface . active high. txframe_pulse o hstl/lvttl 1 n frame pulse output for line interface . active high. rxd[31:0] i hstl/lvttl /lvpecl 32 n 32-bit single ended receive data bus for sonet/sdh link . this bus can be configured as two 16-bit buses in aps operation. rxclk i hstl/lvttl /lvpecl 1n receive clock input from the phy device for line interface . rxclks i hstl/lvttl /lvpecl 1n receive clock input from the slave phy device for sonet/sdh link to support aps . txclkout o hstl/lvttl 1 n transmit clock to physical layer device for line interface . this will be rxclk or the txclki based on t he clock selection in the sonet tx block register. during loopback this is same as the rxclk. txclki i hstl/lvttl /lvpecl 1n input transmit clock from physical layer device for line interface . txd[31:0] o hstl/lvttl 32 n 32-bit single ended transmit data bus for line interface . this bus can be configured as two 16-bit buses in aps operation. sonettx_parou t ohstl/lvttl 1 n sonet tx parity output . can be odd/even parity, as programmed in the sonet/sdh tx block register. sonetrx_parin i hstl/lvttl /lvpecl 1n sonet rx parity input . can be odd/even parity, as programmed in the sonet/sdh rx block register. lfi_n i lvttl 1 y line fault indicator . when low, this signal indicates that the phy has detected loss of optical signal on the sonet/sdh link. overhead bytes access?serial ports clk2mhz o lvttl 1 y toh serial port clock output . tohdout is clocked out on rising edge of this clock and tohdin is latched-in with falling edge of this clock. the frequency is 2.048 mhz, derived from sysclk. clk16mhz o lvttl 1 y poh serial port clock output . pohdout is clocked out on rising edge of this clock and pohdin is latched-in with falling edge of this clock. the frequency is 16.625 mhz, derived from sysclk te1strobe o lvttl 1 y transmit e1 strobe . transmit toh serial port data start indication. active high pulse generated once in every 125 ms. indicates the first bit of e1 byte. te2strobe o lvttl 1 y transmit e2 strobe . active high pulse generated once in every 125 ms. indicates the first bit of e2 byte. tpohstart o lvttl 1 y transmit poh serial port data start indication . active high pulse generated once in every 125 ms. tohsdin i lvttl 1 y transport over head serial port data input . pohsdin i lvttl 1 y path over head serial port data input . re1strobe o lvttl 1 y receive e1 strobe . receive toh serial port data start indication. active high pulse generated once in every 125 ms. indicates that the posic2gvc expects the first bit of the first byte of e1 should accompany the next clock edge. msb is transmitted first. re2strobe o lvttl 1 y receive e2 strobe . active high pulse generated once in every 125 ms. indicates that the posic2gvc expec ts the first bit of the first byte of e2 should accompany the next cl ock edge. msb is transmitted first. rpohstart o lvttl 1 y receive poh serial port data start indication . active high pulse generated once in every 125 ms. indicates that the posic2gvc expects the first bit of the first byte of rpoh should accompany the next clock edge. tohsdout o lvttl 1 y transport over head serial port data output .
confidential cy7c9536b document #: 38-02078 rev. *g page 12 of 46 pohsdout o lvttl 1 y path over head serial port data output . system interface (oif-spi level 3/utopia level 3/hbst) signals (in this section, pos = oif - spi le vel 3, atm = utopia level 3 mode) rval o lvttl 1 n pos: receive data valid (rval) signal. rval indicates the validity of receive data signals. rval will transition low when receive fifo is empty or at the end of a packet. when rval is high, the rdat[31:0], rprty, rmod[1:0], rsop, reop, and rerr signals are valid. when rval is low, the rdat[31:0], rprty, rmod[1:0], rsop, reop, and rerr signals are invalid and must be disregarded. hbst: receive data valid (rdval) signal. the rdata, rbval, rsop, reop, rerr, and raddr are valid when this signal is active. renb i lvttl 1 n pos: receive read enable (renb) signal. the renb signal is used to control the flow of data from the receive fifos. during data transfer, rval must be monitored as it will indicate if the rdat[31:0], rprty, mod[1:0], rsop, reop, rerr and rsx are valid. the system may deassert re nb at anytime if it is unable to accept data from posic2gvc. when renb is sampled low by po sic2gvc, a read is performed from the receive fifo and the rdat[31:0], rprty, rmod[1:0], rsop, reop, rerr, rsx and rval signals are updated on the following rising edge of rfclk. when renb is sampled high by posic2gvc, a read is not performed and the rdat[31:0], rprty, rmod[1:0], rsop, reop, rerr, rsx and rval signals will not updated. atm: enable data transfers (rxenb*) signal enables port selection. hbst: receive data ready (rready_n) signal active low signal, indicates ready to accept data. the device will send valid data 2 clocks after the assertion of this signal. rfclk i lvttl 1 n pos: receive fifo write clock (rfclk). rfclk is used to synchronize data transfer transactions between the link layer device and the posic2 gvc. rfclk may cycle at a rate up to 100 mhz. atm: transfer/interface clock (rxclk) hbst: receive clock (rclk). max 104 mhz receive clock for level-3 operation. all signals are latched out on the rising edge of this clock. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 13 of 46 rdat[31:0] o lvttl 32 n pos: receive packet data bus (rdat[31:0]) the rdat[31:0] bus carries the packet octets that are read from the receive fifo and the in-band port address of the selected receive fifo. rdat[31:0] is considered va lid only when rval is asserted. given the defined data structure, bit 31 is received first and bit 0 is received last. atm: receive cell data bus (rxdata[31:0]) the rdat[31:0] bus carries the cell octets that are read from the receive fifo. rdat[31:0] is consid ered valid only when renb is asserted. given the defined data struct ure, bit 31 is received first and bit 0 is received last rdat[31:0] is updated on the risi ng edge of rclk. this bus is big-endian in format. hbst: receive data bus (rdata[31:0]) 32-bit data bus, the data is valid when rdval signal is active. radd[7:0] o lvttl 8 n hbst: receive port address (raddr[7:0]). when rdval signal is active, this address on this bus indicates port address in raddr[3:0] and tag value in raddr[7:4]. in single-channel mode all 8 bits will contain the tag value. raddr is considered valid only when rdval is asserted rmod[1:0] o lvttl 2 n pos: receive word modulo (rmod[1:0]) signal. rmod[1:0] indicates the number of valid bytes of data in rdat[31:0]. the rmod bus should always be all zero, except during the last double-word transfer of a packet on rdat[31:0]. when reop is asserted, the number of valid packet data bytes on rdat[31:0] is specified by rmod[1:0] rmod[1:0] = ?00? rdat[31:0] valid rmod[1:0] = ?01? rdat[31:8] valid rmod[1:0] = ?10? rdat[31:16] valid rmod[1:0] = ?11? rdat[31:24] valid rmod[1:0] is considered valid only when rval is asserted. in 16-bit mode, only rmod[0] is valid. rmod[0] = ?1? rdat[15:8] valid (16-bit mode) rmod[0] = ?0? rdat[15:0] valid (16-bit mode) hbst: receive data byte valid (rbval[1:0]) signals. this indicates the number of bytes data bytes valid on the rdata bus, 00 = 4 bytes valid, 11 = 1 byte valid. rprty o lvttl 1 n pos: receive parity (rprty) signal. the receive parity (rprty) signal indicates the parity calculated over the rdat bus. rprty supports both odd and even parity. atm: receive parity (rxprty) signal. data bus odd parity. hbst: receive bus parity (rparity) signal. receive bus parity, even/odd parity calculated on the data bus alone or on all the bus signals (rdata, raddr, rdval, rbval, rsop, reop, rerr). pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 14 of 46 rerr o lvttl 1 n pos: receive error indicator (rerr) signal. rerr is used to indicate that the current packet is aborted and should be discarded. rerr shall only be asserted when reop is asserted. conditions that can cause rerr to be set may be, but are not limited to, fifo overflow, abort sequence detection and fcs error. rerr is considered valid only when rval is asserted. hbst: receive error indicator (rerr) signal. a high indicates the current packet or cell has error. reop o lvttl 1 n pos: receive end of packet (reop) signal. reop is used to delineate the packet boundaries on the rdat bus. when reop is high, the end of the packet is present on the rdat bus. reop is required to be present at the end of every packet and is considered valid only when rval is asserted. hbst: end of packet/cell (reop) signal. a high indicates the end of packet or cell. rsop/rsoc o lvttl 1 n pos: receive start of packet (rsop) signal. rsop is used to delineate the packet boundaries on the rdat bus. when rsop is high, the start of the packet is present on the rdat bus. rsop is required to be present at the start of every packet and is considered valid when rval is asserted. atm: receive start of cell (rxsoc). this signal marks the start of a cell structure on the rxdata bus. the first word of the cell structure is present on the rxdata[31:0] bus when rxsoc is high. rxsoc is updated on the rising edge of rxclk. hbst: receive start of packet/cell (rsop) signal. a high indicates start of packet or start of cell. rca o lvttl 1 n atm: utopia receive cell available (rxclav). rxclav will be asserted, whenever a minimum of 1 cell of data is available in the receive fifo. hbst: receive fifo available (rstfa) signal. rstfa indicates when data is available in the receive fifo. rstfa will be asserted, whenever receive fifo has at least predefined number of bytes to be read (the nu mber of bytes is user program- mable). rstfa is updated on the rising edge of rclk. rsx o lvttl 1 n pos: receive start of transfer signal. rsx indicates when the in-band port address is present on the rdat bus. when rsx is high and rval is low, the value of rdat[7:0] is the address of the receive fifo to be selected by posic2gvc. subsequent data transfers on the rdat bus will be from the port as specified by the in band address. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 15 of 46 tfclk i lvttl 1 n pos: transmit fifo write clock (tfclk). tfclk is used to synchronize data transfer transactions between the link layer device and posic2gvc. tfclk may cycle at a rate up to 100 mhz. atm: transfer/interface clock (txclk). hbst: transmit clock (tclk). max 104 mhz transmit clock for level-3 operation. all transmit signals are sampled on rising edge of the clock. terr i lvttl 1 n pos: transmit error indica tor (terr) signal. terr is used to indicate that the current packet should be aborted. when terr is set high, the current packet is aborted. terr should only be asserted when teop is asserted. hbst: transmit error indica tor (terr) signal. a high indicates the current packet or cell has error. tenb i lvttl 1 n pos: transmit write enable (tenb) signal. the tenb signal is used to control the flow of data to the transmit fifos. when tenb is high, the tdat, tmod, tsop, teop, and terr signals are invalid and are ignored by posic2gvc. the tsx signal is valid and is processed by posic2gvc when tenb is high. when tenb is low, the tdat, tmod, tsop, teop and terr signals are valid and are processe d by posic2gvc. also, the tsx signal is ignored by posic2gvc when tenb is low. atm: transmit write enable (txenb*). this signal is an active low input which is used to initiate writes to the transmit fifos. when txenb* is sampled high, the information sampled on the txdata, txprty, and txsoc signals are invalid. when txenb* is sampled low, the information sampled on the txdata, txprty, and txsoc signals are valid and are written into the transmit fifo. txenb* is sampled on the rising edge of txclk. hbst: transmit data valid (tdval_n) signal. the tdval_n signal is used to contro l the flow of data to the transmit fifos. when tdval_n is high, the tdata, tbval, tsop, taddr, tsop, teop, and terr signals are valid and are processed by posic2gvc. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 16 of 46 tdat[31:0] i 32 n pos: transmit packet data bus (tdat) bus. this bus carries the packet octets that are written to the selected transmit fifo and the in-band port address to select the desired transmit fifo. the tdat bus is considered valid only when tenb is simultaneously asserted. data is transmitted in big endian order on tdat[31:0]. given the defined data structure, bit 31 is tr ansmitted first and bit 0 is transmitted last. atm: transmit data bus (txdata) bus. this data bus carries the atm cell. data on this bus is valid only if txenb* is high. txdata[31:0] is three-stated if txenb* is low. txdata[31:0] is updated on the rising edge of txclk. hbst: transmit data bus (tdata) bus. 32-bit data bus. the data is valid when tdval_n signal is active. tprty i lvttl 1 n pos: transmit bus parity (tprty) signal. the transmit parity (tprty) signal i ndicates the parity calculated over the tdat bus. tprty is considered valid only when tenb is asserted. tprty is supported for both even and odd parity. atm: transmit bus parity (txprty). this signal indicates the parity on the txdata bus. a parity error is indicated by a status bit and a maskable interrupt. txprty is considered valid only when txenb* is simultaneously asserted. txprty is sampled on the rising edge of txclk. hbst: transmit bus parity (tparity) signal. even/odd parity calculated on the data bus alone or on all the bus signals (tdata, taddr, tdval_n, tbval, tsop, teop, and terr). tadd[3:0] i lvttl 4 n pos: transmit address bus (ptadr) bus. address driven by link layer to poll and select the appropriate posic2gvc channel (port). the value for the transmit and receive portions of a channel should be ident ical. address 31 indicates a null port. atm: transmit address bus (txaddr) bus. address of posic2gvc channel being selected. hbst: port address (taddr) bus. address driven by the link layer to indicate the port address of current data transfer. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 17 of 46 tmod[1:0] i lvttl 2 n pos: transmit word modulo (tmod[1:0]) signal. tmod[1:0] indicates the number of valid bytes of data in tdat[31:0]. the tmod bus should always be all zero, except during the last double-word transfer of a packet on tdat[31:0]. when teop is asserted, the number of valid packet data bytes on tdat[31:0] is specified by tmod[1:0]. tmod[1:0] = ?00? tdat[31:0] valid tmod[1:0] = ?01? tdat[31:8] valid tmod[1:0] = ?10? tdat[31:16] valid tmod[1:0] = ?11? tdat[31:24] valid in 16-bit mode, only tmod[0] is valid. tmod[0] = ?1? tdat[15:8] valid (16-bit mode) tmod[0] = ?0? tdat[15:0] valid (16-bit mode) hbst: transmit byte valid (tbval[1:0]) signals. this indicates the number of bytes data bytes on the tdata bus, 00 = 4 bytes valid, 11 = 1 byte valid. tsop i lvttl 1 n pos: transmit start of packet (tsop) signal. tsop is used to delineate the packet boundaries on the tdat bus. when tsop is high, the start of the packet is present on the tdat bus. tsop is required to be present at the beginning of every packet and is considered valid only when tenb is asserted. atm: transmit start of cell (txsoc) signal. this signal marks the start of a cell structure on the txdata bus. txsoc must be present for each cell . txsoc is considered valid only when txenb* is simultaneously asserted. txsoc is sampled on the rising edge of txclk. hbst: transmit start of packet (tsop) signal. a high indicates the start of packet or start of cell. teop i lvttl 1 n pos: transmit end of pa cket (teop) signal. teop is used to delineate the packet boundaries on the tdat bus. when teop is high, the end of the packet is present on the tdat bus. teop is required to be present at the end of every packet and is considered valid only when tenb is asserted. hbst: transmit end of pa cket (teop) signal. a high indicates the end of packet or end of cell. dtca[3:0] o lvttl 4 n pos: transmit packet available (dtpa) bus. this signal provides direct status indi cation the fill status of the transmit fifo. note that, regardless of what fill level tpa is set to indicate ?full? at, the transmit packet processo r can store 256 bytes of data. when dtpa transitions high, it i ndicates that the transmit fifo has enough room to store a configurabl e number of data bytes. this transition level is select ed in the cpu programmable registers. when tpa transitions low, it indicate s that the transmit fifo is either full or near full as specified by the cpu programmable registers. dtpa is updated on the rising edge of tfclk. hbst: polled fifo available status (tfast) bus. when the signal tsofst is active, the status of channels 0,4,8,12 is given first followed by 1,5,9,13 and 2,6,10,14 and the last 3,7,11,15. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 18 of 46 stpa o lvttl 1 n pos: selected channel transmit packet available (stpa) signal. stpa transitions high when a predefined minimum number of bytes are available in the selected transmit fifo. once high, stpa indicates that transmit fifo is not full. when stpa transitions low, it optionally indicates that transmit fifo is full or near full (user programmable). stpa always provides status indication for the selected channel in order to avoid fifo overflows while polling is performed. stpa is three-stated when tenb is deasserted in the previous cycle. stpa is also deasserted when either the null-port address (0x1f) or an address not matching the posic2gvc address is presented on the tadr[3:0] signals when tenb is sampled high (has been de-asserted during the previous clock cycle). stpa is mandatory only if packet-leve l transfer mode is supported. it is not be driven in byte-level mode. atm: there is no corresponding pin definition in atm mode, however, this pin will output the same signal as stpa in pos mode hbst: fifo available status (tstfa) signal. fifo available status of the selected port is reflected on this pin two clocks after detecting the port address when the tdval signal is active. ptca o lvttl 1 n pos: polled-port transmit packet available (ptpa) signal. ptpa transitions high when a predefined (user-programmable) minimum number of bytes are available in the polled transmit fifo. once high, ptpa indicates that th e transmit fifo is not full. when ptpa transitions low, it optionally indicates that transmit fifo is full or near full (user-programmable). ptpa allows polling the posic2gvc channel selected by tadr[3:0] when tenb is asserted. ptpa is driven by a posic2gvc when its address is polled by tadr[3:0]. posic2gvc will three-state ptpa when either the null-port address (0x1f) or an address not matching posic2gvc is provided on tadr[3:0]. ptpa is mandatory only if in packet-level transfer mode. it will not be driven in byte-level mode. atm: utopia transmit cell available (txclav) the txclav signal indicates when a cell is available in the transmit fifo for the port polled by txaddr [3:0] when txenb* is asserted. when high, txclav indicates that the corresponding transmit fifo is not full and a complete cell may be written. when txclav goes low, it can be configured to indicate either that the corresponding transmit fifo is near full or that the corres ponding transmit fifo is full. txclav is three-stated when either the nu ll-port address (0x1f) or an address not matching the address space set is latched from the txaddr[4:0] inputs when txenb* is high. txclav is updated on the rising edge of txclk. hbst: fifo available status on tfast bus (tsofst) signal. active high pulse indicates the start of fifo available status on tfast bus. this signal is repea ted once in every four clocks. tsx i lvttl 1 n pos: transmit start of transfer (tsx) signal. tsx indicates inband port address on the tdat bus. when tenb is high and tsx is asserted (high), the value of tadr[3:0] is the address of transmit fifo selected. tsx is valid only when tenb is deasserted. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 19 of 46 memory interface for virtual concatenation ad [18:0] o lvttl 19 n synchronous address inputs used to address up to six 512k x 36 nobl? srams. sampled at the rising edge of the clk. we o lvttl 1 n synchronous write enable input, active low. this must be sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence adv/ld o lvttl 1 n synchronous advance/load input this pin is used to advance the on- chip (sram?s) address counter or load a new address. when high (and cen is asserted low) the internal burst counter of sram is advanced. when low, a new address is loaded into the sram for an access. after being deselected, adv/ld should be driven low in order to load a new address. ce1 o lvttl 1 n synchronous chip enable 1, active low. sampled on the rising edge of clk. used to select/deselect first bank of the nobl memory. ce2 o lvttl 1 n synchronous chip enable 2, active low. sampled on the rising edge of clk. used to select/deselect second bank of the nobl memory. ce3 o lvttl 1 n synchronous chip enable 3, active low. sampled on the rising edge of clk. used to select/deselect third bank of the nobl memory. oe o lvttl 1 n asynchronous output enable, permanently active low. this pin is internally grounded to the vss2 bus. the pin should be connected to th e oen input of the nobl memories, or alternatively, left unconnected if the nobl oen input is directly grounded on the board. dq1[31:0] i/o lvttl 32 n synchronous bidirectional data i/o lines for sram1. as inputs to sram, these pins feed into a data register that is triggered by the rising edge of clk. as output s from sram, they deliver the data contained in the memory location specified by a [18:0] during the previous clock rise of the read cy cle. when oe is asserted low, the pins can behave as outputs from sram. when high, dq1 [31:0] are placed in a three-state conditio n by the sram. the outputs are automatically three-stated during t he data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe. dq2 [31:0] i/o lvttl 32 n synchronous bidi rectional data i/o lines for sram2. as inputs to sram, these pins feed into a data register that is triggered by the rising edge of clk. as output s from sram, they deliver the data contained in the memory location specified by a [18:0] during the previous clock rise of the read cy cle. when oe is asserted low, the pins can behave as outputs from sram. when high, dq2 [31:0] are placed in a three-state conditio n by the sram. the outputs are automatically three-stated during t he data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe. cpu interface signals cpuclk i lvttl 1 y cpu clock . cpusel i lvttl 1 y used to select between intel and motorola cpu . ?0? = motorola, ?1? = intel cputs_n/cpuads_n i lvttl 1 y transfer start . active low cpuwrrd i lvttl 1 y write/read signal . in intel mode, ac tive high for write operation. in motorola mode, active low for write operation. pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 20 of 46 cputa_n o lvttl 1 y transfer acknowledge/data ready . active low. open drain output cpublast_n / cpubdip_n ilvttl 1 y used with burst transaction . active low. cpuint/ o lvttl 1 y interrupt to cpu . active low. cpuclkfail o lvttl 1 y cpu clock fail signa l. when low indicates failure of cpu clock. cpuad[31:0] i/o lvttl 32 y address/data bus . chipsel i lvttl 1 y the chip select signal for posic2gvc. active low . mode i lvttl 1 y 32-/16-bit mode select . ?0? = 32-bit mode, ?1? otherwise. jtag interface signals tck i lvttl 1 jtag mode: test clock trst i lvttl 1 jtag mode: test reset tdi i lvttl 1 jtag mode: test input tms i lvttl 1 jtag mode: test mode select. pull-down to gnd during normal operation. tdo o lvttl 1 jtag mode: test output miscellaneous signals vref i vref 4 n reference voltage for hstl and lvpecl inputs . set to gnd during lvttl mode of operation. rst_n i lvttl 1 y active low asynchronous reset input . sysclk i lvttl 1 n 133-mhz system clock . clkout o lvttl 1 n sysclk out . used as clk for the virtual concatenation memories rstout_n o lvttl 1 y reset out, active low . test[2:0] i lvttl 3 y test mode selection signals . pull-up to ?1? during normal operation. scan_ena i lvttl 1 y scan enable pin . active high. pull-down to ?0? for normal operation posic_oen i lvttl 1 y the posic2gvc output en able (posic_oen) signal . when set to logic one, all posic2gvc outputs (except cputa_n and clkout) are held three-state. when posic_oen is set to logic zero, all inter- faces are enabled. pull-down to ?0? for normal operation. total io pins 336 power: vcc pad+core p85 power: gnd pad+core p83 total 504 i/os: 336; power: 168 pin description (continued) signal name i/o pad type pins jtag pin description
confidential cy7c9536b document #: 38-02078 rev. *g page 21 of 46 pin assignment pin assignment table signal ball pin type rdat<0> f3 lvttl_out rdat<1> f2 lvttl_out rdat<10> j6 lvttl_out rdat<11> j5 lvttl_out rdat<12> j4 lvttl_out rdat<13> j3 lvttl_out rdat<14> j2 lvttl_out rdat<15> k5 lvttl_out rdat<16> k4 lvttl_out rdat<17> k3 lvttl_out rdat<18> k2 lvttl_out rdat<19> l5 lvttl_out rdat<2> g6 lvttl_out rdat<20> l4 lvttl_out rdat<21> l3 lvttl_out rdat<22> l2 lvttl_out rdat<23> l1 lvttl_out rdat<24> m5 lvttl_out rdat<25> m4 lvttl_out rdat<26> m3 lvttl_out rdat<27> m2 lvttl_out rdat<28> m1 lvttl_out rdat<29> n5 lvttl_out rdat<3> g5 lvttl_out rdat<30> n4 lvttl_out rdat<31> n3 lvttl_out rdat<4> g3 lvttl_out rdat<5> g2 lvttl_out rdat<6> h6 lvttl_out rdat<7> h5 lvttl_out rdat<8> h4 lvttl_out rdat<9> h2 lvttl_out radd<0> n2 lvttl_out radd<1> n1 lvttl_out radd<2> p5 lvttl_out radd<3> p4 lvttl_out radd<4> p3 lvttl_out radd<5> p2 lvttl_out radd<6> r5 lvttl_out radd<7> r4 lvttl_out rerr t4 lvttl_out rmod<0> r2 lvttl_out rmod<1> r3 lvttl_out rprty t5 lvttl_out reop t2 lvttl_out rca u4 lvttl_out
confidential cy7c9536b document #: 38-02078 rev. *g page 22 of 46 rsop/rsoc t3 lvttl_out rsx u5 lvttl_out rval u1 lvttl_out rfclk v3 lvttl_in renb u2 lvttl_in tadd<0> ae3 lvttl_in tadd<1> ae4 lvttl_in tadd<2> af3 lvttl_in tadd<3> ag4 lvttl_in tdat<0> u3 lvttl_in tdat<1> v1 lvttl_in tdat<10> y2 lvttl_in tdat<11> y3 lvttl_in tdat<12> y4 lvttl_in tdat<13> y5 lvttl_in tdat<14> aa2 lvttl_in tdat<15> aa3 lvttl_in tdat<16> aa4 lvttl_in tdat<17> aa5 lvttl_in tdat<18> aa6 lvttl_in tdat<19> ab2 lvttl_in tdat<2> v2 lvttl_in tdat<20> ab3 lvttl_in tdat<21> ab4 lvttl_in tdat<22> ab6 lvttl_in tdat<23> ac2 lvttl_in tdat<24> ac3 lvttl_in tdat<25> ac4 lvttl_in tdat<26> ac5 lvttl_in tdat<27> ac6 lvttl_in tdat<28> ad2 lvttl_in tdat<29> ad4 lvttl_in tdat<3> v4 lvttl_in tdat<30> ad5 lvttl_in tdat<31> ae2 lvttl_in tdat<4> v5 lvttl_in tdat<5> w1 lvttl_in tdat<6> w2 lvttl_in tdat<7> w3 lvttl_in tdat<8> w4 lvttl_in tdat<9> w5 lvttl_in terr af5 lvttl_in tenb ae6 lvttl_in tprty ag5 lvttl_in tsop af6 lvttl_in teop ad7 lvttl_in tsx ag6 lvttl_in pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 23 of 46 tfclk ae7 lvttl_in tmod<0> af7 lvttl_in tmod<1> ad8 lvttl_in dtca<0> ah6 lvttl_out dtca<1> ae8 lvttl_out dtca<2> ag7 lvttl_out dtca<3> ah7 lvttl_out stpa ad9 lvttl_out ptca ag8 lvttl_out cputa_n ae9 open drain output cpuclkfail ah8 lvttl_out cpuint af9 lvttl_out cpuad<0> ag9 lvttl_io cpuad<1> ah9 lvttl_io cpuad<10> aj11 lvttl_io cpuad<11> ae12 lvttl_io cpuad<12> af12 lvttl_io cpuad<13> ah12 lvttl_io cpuad<14> ae13 lvttl_io cpuad<15> af13 lvttl_io cpuad<16> ag13 lvttl_io cpuad<17> ah13 lvttl_io cpuad<18> aj13 lvttl_io cpuad<19> ae14 lvttl_io cpuad<2> ae10 lvttl_io cpuad<20> af14 lvttl_io cpuad<21> ag14 lvttl_io cpuad<22> ae15 lvttl_io cpuad<23> af15 lvttl_io cpuad<24> ag15 lvttl_io cpuad<25> ah15 lvttl_io cpuad<26> ae16 lvttl_io cpuad<27> af16 lvttl_io cpuad<28> ah16 lvttl_io cpuad<29> ae17 lvttl_io cpuad<3> af10 lvttl_io cpuad<30> af18 lvttl_io cpuad<31> ag18 lvttl_io cpuad<4> ag10 lvttl_io cpuad<5> ah10 lvttl_io cpuad<6> ae11 lvttl_io cpuad<7> af11 lvttl_io cpuad<8> ag11 lvttl_io cpuad<9> ah11 lvttl_io cpusel ag16 lvttl_in mode ae18 lvttl_in cputs_n aj17 lvttl_in pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 24 of 46 cpuwrd ag19 lvttl_in cpublast_n ah17 lvttl_in chipsel af19 lvttl_in scan_ena ag17 lvttl_in posic_oen ae19 lvttl_in cpuclk af20 lvttl_in rst_n ah18 lvttl_in test<0> ae20 lvttl_in test<1> ag21 lvttl_in test<2> ah19 lvttl_in tck af21 lvttl_in sysclk ae21 lvttl_in tdi ag20 lvttl_in tms ad21 lvttl_in trst af22 lvttl_in tdo ad22 lvttl_out rstout_n ag23 lvttl_out clkout c16 lvttl_out tohsdin ae22 lvttl_in pohsdin ag22 lvttl_in te1strobe ah24 lvttl_out te2strobe af23 lvttl_out tpohstart ah25 lvttl_out rpohstart ad23 lvttl_out clk2mhz af24 lvttl_out clk16mhz ae24 lvttl_out re1strobe af25 lvttl_out re2strobe ag25 lvttl_out pohsdout ae26 lvttl_out tohsdout ag26 lvttl_out txframe_pulse ae27 hstl/lvttl_out sonettx_parout ad 25 hstl/lvttl_out txd<0> ad28 hstl/lvttl_out txd<1> ad27 hstl/lvttl_out txd<10> ab26 hstl/lvttl_out txd<11> ab25 hstl/lvttl_out txd<12> ab24 hstl/lvttl_out txd<13> aa28 hstl/lvttl_out txd<14> aa27 hstl/lvttl_out txd<15> aa26 hstl/lvttl_out txd<16> aa25 hstl/lvttl_out txd<17> aa24 hstl/lvttl_out txd<18> y29 hstl/lvttl_out txd<19> y28 hstl/lvttl_out txd<2> ad26 hstl/lvttl_out txd<20> y27 hstl/lvttl_out txd<21> w27 hstl/lvttl_out pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 25 of 46 txd<22> w26 hstl/lvttl_out txd<23> w25 hstl/lvttl_out txd<24> v28 hstl/lvttl_out txd<25> v27 hstl/lvttl_out txd<26> v26 hstl/lvttl_out txd<27> v25 hstl/lvttl_out txd<28> u29 hstl/lvttl_out txd<29> u28 hstl/lvttl_out txd<3> ac28 hstl/lvttl_out txd<30> t28 hstl/lvttl_out txd<31> t27 hstl/lvttl_out txd<4> ac27 hstl/lvttl_out txd<5> ac26 hstl/lvttl_out txd<6> ac25 hstl/lvttl_out txd<7> ac24 hstl/lvttl_out txd<8> ab28 hstl/lvttl_out txd<9> ab27 hstl/lvttl_out txclkout w28 hstl/lvttl_out txclki r27 hstl/lvttllvpecl_in vref u27 0.75v/2.0v input vref p26 0.75v/2.0v input vref m25 0.75v/2.0v input vref g27 0.75v/2.0v input rxclk n28 hstl/lvtt/llvpecl_in rxclks h26 hstl/lvttl/lvpecl_in rxd<0> h27 hstl/ lvttl/lvpecl_in rxd<1> h28 hstl/ lvttl/lvpecl_in rxd<10> k29 hstl/lvttl/lvpecl_in rxd<11> l25 hstl/lvttl/lvpecl_in rxd<12> l26 hstl/lvttl/lvpecl_in rxd<13> l27 hstl/lvttl/lvpecl_in rxd<14> l28 hstl/lvttl/lvpecl_in rxd<15> m26 hstl/lvttl/lvpecl_in rxd<16> m27 hstl/lvttl/lvpecl_in rxd<17> m28 hstl/lvttl/lvpecl_in rxd<18> n25 hstl/lvttl/lvpecl_in rxd<19> n26 hstl/lvttl/lvpecl_in rxd<2> j24 hstl/lvttl/lvpecl_in rxd<20> n27 hstl/lvttl/lvpecl_in rxd<21> n29 hstl/lvttl/lvpecl_in rxd<22> p25 hstl/lvttl/lvpecl_in rxd<23> p27 hstl/lvttl/lvpecl_in rxd<24> p28 hstl/lvttl/lvpecl_in rxd<25> r25 hstl/lvttl/lvpecl_in rxd<26> r26 hstl/lvttl/lvpecl_in rxd<27> r28 hstl/lvttl/lvpecl_in rxd<28> t25 hstl/lvttl/lvpecl_in pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 26 of 46 rxd<29> t26 hstl/lvttl/lvpecl_in rxd<3> j25 hstl/lvttl/lvpecl_in rxd<30> u25 hstl/lvttl/lvpecl_in rxd<31> u26 hstl/lvttl/lvpecl_in rxd<4> j26 hstl/lvttl/lvpecl_in rxd<5> j27 hstl/lvttl/lvpecl_in rxd<6> j28 hstl/lvttl/lvpecl_in rxd<7> k25 hstl/lvttl/lvpecl_in rxd<8> k26 hstl/lvttl/lvpecl_in rxd<9> k28 hstl/lvttl/lvpecl_in sonetrx_parin h25 hs tl/lvttl/lvpecl_in lfi_n h24 lvttl_in rxframe_pulse f27 hstl/lvttl/lvpecl_in dq1<0> e27 lvttl_io dq1<1> d27 lvttl_io dq1<10> d24 lvttl_io dq1<11> c24 lvttl_io dq1<12> b24 lvttl_io dq1<13> f23 lvttl_io dq1<14> d23 lvttl_io dq1<15> c23 lvttl_io dq1<16> b23 lvttl_io dq1<17> f22 lvttl_io dq1<18> e22 lvttl_io dq1<19> c22 lvttl_io dq1<2> g26 lvttl_io dq1<20> f21 lvttl_io dq1<21> e21 lvttl_io dq1<22> d21 lvttl_io dq1<23> c21 lvttl_io dq1<24> b21 lvttl_io dq1<25> e20 lvttl_io dq1<26> c20 lvttl_io dq1<27> b20 lvttl_io dq1<28> e19 lvttl_io dq1<29> b19 lvttl_io dq1<3> f26 lvttl_io dq1<30> b18 lvttl_io dq1<31> a18 lvttl_io dq1<4> e26 lvttl_io dq1<5> f25 lvttl_io dq1<6> d25 lvttl_io dq1<7> c25 lvttl_io dq1<8> g24 lvttl_io dq1<9> e24 lvttl_io ce1 b17 lvttl_out ce2 d19 lvttl_out pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 27 of 46 ce3 a17 lvttl_out we b16 lvttl_out oe d18 lvttl_out adv/ld c15 lvttl_out ad<0> d17 lvttl_out ad<1> c17 lvttl_out ad<10> d13 lvttl_out ad<11> c13 lvttl_out ad<12> a13 lvttl_out ad<13> d12 lvttl_out ad<14> c12 lvttl_out ad<15> b12 lvttl_out ad<16> a12 lvttl_out ad<17> c11 lvttl_out ad<18> b11 lvttl_out ad<2> e16 lvttl_out ad<3> d16 lvttl_out ad<4> e15 lvttl_out ad<5> d15 lvttl_out ad<6> e14 lvttl_out ad<7> c14 lvttl_out ad<8> b14 lvttl_out ad<9> e13 lvttl_out dq2<0> e12 lvttl_io dq2<1> e11 lvttl_io dq2<10> c9 lvttl_io dq2<11> b9 lvttl_io dq2<12> f8 lvttl_io dq2<13> e8 lvttl_io dq2<14> c8 lvttl_io dq2<15> b8 lvttl_io dq2<16> f7 lvttl_io dq2<17> e7 lvttl_io dq2<18> d7 lvttl_io dq2<19> c7 lvttl_io dq2<2> d11 lvttl_io dq2<20> b7 lvttl_io dq2<21> e6 lvttl_io dq2<22> d6 lvttl_io dq2<23> c6 lvttl_io dq2<24> f5 lvttl_io dq2<25> d5 lvttl_io dq2<26> c5 lvttl_io dq2<27> f4 lvttl_io dq2<28> c4 lvttl_io dq2<29> e3 lvttl_io dq2<3> e10 lvttl_io pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 28 of 46 dq2<30> e2 lvttl_io dq2<31> d2 lvttl_io dq2<4> d10 lvttl_io dq2<5> c10 lvttl_io dq2<6> b10 lvttl_io dq2<7> f9 lvttl_io dq2<8> e9 lvttl_io dq2<9> d9 lvttl_io vss1 a1, b1, ae1, aj1, aj2, ag12, a2, d3, ad3, ah4, aj4, a4, ah5, ah14, c18, aj18, aj19, ah20, ah21, b22, ah23, ag24, b25, ah26, b27, k27, aj28, af28, a28, d28, f28, a29, b29, j29, m29, p29, aj29 core + input pin gnd vss2 g1, j1, p1, t1, aa1, ac1, b2, c3, aj3, e4, g4, a6, b6, aj7, af8, a9, aj9, a11, aj12, b13, aj14, a16, aj16, e17, c19, a20, aj21, aj22, a23, ae23, aj23, a25, a27, af27, aj27, ah28, c29, d29, f29, r29, w29, ac29, ae29, af29, ah29, y25 output pin gnd v cc1 d1, af1, ag2, c2, b3, ah3, d4, af4, b5, e5, aj5, d20, d22, e25, a26, c26, d26, af26, aj26, ah27, ae28, e29, g29, h29, l29 core voltage, 1.8v v cc2 ad1, ag1, ah1, af 2, ah2, ag3, b4, ab5, ae5, a7, a10, a14, af17, a21, a22, ah22, c28, e28, g28 lvttl input pin power supply, 3.3v v cc3 c1, e1, f1, h1, k1, r1, y1, ab1, a3, h3, a5, aj6, a8, d8, aj8, aj10, d14, a15, b15, aj15, e18, a19, aj20, e23, a24, aj24, g25, aj25, b26, c27, ag27, b28, ag29 lvttl output pin power supply, 3.3v v cc5 ae25, ag28, t29, v29, aa29, ab29, ad29, y26 hstl output pin power supply, 1.5v/3.3v pin assignment table (continued) signal ball pin type
confidential cy7c9536b document #: 38-02078 rev. *g page 29 of 46 maximum ratings (above which the useful life may be impaired. for user guide-lines, not tested.) operating range specifies temperature and voltage boundary conditions for safe operation of the device. operation outside these boundary may affect the performance and life of the device. operating range dc specifications table 3. device absolute maximum ratings parameter value unit case temperature ?40 to 85 c storage temperature 150 c absolute maximum junction temperature 125 c lead temperature 220 c supply voltage v cc1 for core 2.43 v supply voltage v cc2 for lvttl inputs 4.785 v supply voltage v cc3 for lvttl outputs 4.785 v supply voltage v cc5 for hstl/lvttl outputs 4.785 v v ref v cc + 0.3 v all inputs values v cc + 0.3 v static discharge voltage (esd) from jesd22-a114 >2000 v latch-up current >200 ma maximum output short circuit current fo r all i/o configurations. (vout = 0v) [18] ?100 ma table 4. operating range range ambient temperature v cc1 v cc5 ( hstl) v cc2 , v cc3 , v cc5 commercial 0c to +70c 1.71v to 1.89v 1.425v to 1. 575v 3.135v to 3.465v industrial ?40c to +85c 1.71v to 1.89v 1.425v to 1. 575v 3.135v to 3.465v table 5. dc specifications parameter description test conditions min. max. unit v cc1 power supply for core 1.71 1.89 v v cc2 power supply for lvttl inputs 3.135 3.465 v v cc3 power supply for lvttl outputs 3.135 3.465 v v cc5 power supply for hstl/lvttl outputs 1.425/3.135 1.575/3.465 v v ref(hstl) reference voltage for hstlinputs 0.68 0.9 v v ref(lvpecl) reference voltage for lvpecl inputs v cc2 ? 1.4 v cc2 ? 1.2 v i cc1 v cc1 supply current ? 1 a i cc2 v cc2 supply current ? 0.1 a i cc3 v cc3 supply current 20-pf capacitive load ? 0.75 a i cc5 v cc5 supply current for lvttl output 20-pf capacitive load ? 0.28 a v cc5 supply current for hstl outp ut 20-pf capacitive load ? 0.017 a pw [19] total chip power 20-pf capacitive load 4.58 watt note: 18. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. tested initia lly and after any design or process changes that may affect these parameters. 19. consult factory for power consumption with external termination resistors.
confidential cy7c9536b document #: 38-02078 rev. *g page 30 of 46 note: 20. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. tested initia lly and after any design or process changes that may affect these parameters. i os [20] output short circuit current for all i/o configurations. see note below. v out = 0v ?20 ?100 ma lvttl i/os v oht output high voltage all v cc = min. i oh = ?8.0 ma 2.4 ? v v olt output low voltage all v cc = min. i ol = 8.0 ma -0.4v v iht input high voltage 2.0 v cc2 + 0.3 v v ilt input low voltage ?0.3 0.8 v i iht input high current all v cc = max., v in = v cc2 ?10 a i ilt input low current all v cc = max., v in = 0v ? ?10 a hstl i/os v ref reference voltage 0.68 0.9 v oh(dc) output high voltage all v cc = min. i oh = ?8.0 ma v cc5 ? 0.4 ? v v ol(dc) output low voltage all v cc = min. i ol = 8.0 ma ?0.4v v oh(ac) output high voltage v cc5 ? 0.5 v v ol(ac) output low voltage ? 0.5 v v ih(dc) input high voltage v ref + 0.1 - v v il(dc) input low voltage ? v ref ? 0.1 v v ih(ac) input high voltage v cc1 = 1.71v v ref + 0.2 v v il(ac) input low voltage v cc1 = 1.89v ? v ref ? 0.2 v i ihh input high current all v cc = max. v in = v cc1 ?10 a i ilh input low current all v cc = max. v in = 0v ? ?10 a lvpecl inputs v ref reference voltage v cc2 ? 1.4 v cc2 ? 1.2 v v ih(dc) input high voltage v cc2 ? 1.1 ? v v il(dc) input low voltage ? v cc2 ? 1.5 v v ih(ac) input high voltage v cc2 ? 1.0 v v il(ac) input low voltage ? v cc2 ? 1.6 v i ihh input high current all v cc = max. v in = v cc2 ?10 a i ilh input low current all v cc = max. v in = 0v ? ?10 a table 5. dc specifications (continued) parameter description test conditions min. max. unit
confidential cy7c9536b document #: 38-02078 rev. *g page 31 of 46 ac test loads and waveform gnd < 1ns v th = 1.4v 3.0v 2.0v 0.8v 2.0v 0.8v v th = 1.4v < 1ns (a) lvttl input test waveform v ihl < 1ns v th = 0.75v v ihh 80% 20% 80% 20% v th = 0.75v < 1ns (b) hstl input test waveform v il < 1ns v th = 2.0v v ih 80% 20% 80% 20% v th = 2.0v < 1ns (c) lvpecl input test waveform . c l 1.4v r1 (a) lvttl ac test load output r1=125 ohm c l < 20pf test point 50 ohm t-line . c l 1.5v r1 r2 (b) hstl ac test load output r1=100 ohm r2=100 ohm c l < 12pf 50 ohm t-line test point output 3.3v r2 r1 r3 c l (c) lvpecl-compliant termination r1=125 ohm r2=79 ohm r3=138 ohm c l = 7pf 50 ohm t-line test point
confidential cy7c9536b document #: 38-02078 rev. *g page 32 of 46 reset requirements asserting the rst_n signal will asynchronously reset all sequential elements of posic2 gvc. even though the reset is treated as asynchronous signal , it is recommended that a minimum of 1-ms-wide active low rst_n is applied after all power supplies have stabilized. power-up requirements when hstl i/o is used, v cc1 , v cc2 , and v cc3 need to be powered up first before v cc5 supply. v cc5 shall be powered up at least 300ms after the last of the other power supplies. there is no particular power-up sequence requirements among v cc1 , v cc2 , and v cc3 in this case. there is no particular power-up sequence requirements among v cc1 , v cc2 , v cc3 , and v cc5 if hstl i/o is not used. rst_n needs to be activated until all the power supplies have stabilized. ac and timing specifications the posic2gvc device interfaces to industry standard peripheral devices or buses. hence the posic2gvc pin timing parameters are governed by the interface requirements of the peripherals or the relevant standards. ta ble 6 details the timing requirements. ac specifications table 6. posic2gvc pin timing requirements posic2gvc pin group peripheral device/bus standard compatible/suggested part number reference/remarks line interface 16-/8-bit hstl/single-ended lvpecl interface cys25g0101dx refer phy data sheet overhead bytes access ? serial ports lvttl described in this document memory interface lvttl cy7c1370b/c or cy7c1464v33 (min. 200-mhz grade) compatible to nobl? or equivalent memory chip system interface utopia level 3/ oif-spi level3 hbst atm forum: btd-phy-ul3-01.05 saturn group: pmc-980495 issue described in this document host cpu interface 16-/32-bit cp u interface lvttl compatible with intel/motorola cpus table 7. line interface timing parameter values parameter description min. max. unit f ts [21] txclkout, txclki frequency (must be frequency coherent to rxclk when used as the transmit pll clock source). f ts nominal (f tsn ) can be 155.52 mhz, 77.76 mhz, 38.88 mhz, 19.44 mhz; depends on the bus width and line rate used. f tsn * (1 ? 0.65%) f tsn * (1 + 0.65%) mhz t txclkip [21] txclki period 1/(f ts max.) 1/(f ts min.) ns t txclkid txclki duty cycle 43 57 % t txclkp [21] txclkout period 1/(f ts max.) 1/(f ts min.) ns t txclkd [21] txclkout duty cycle 40 60 % t txclkr [22] txclkout rise time 0.3 1.5 ns t txclkf [22] txclkout fall time 0.3 1.5 ns t txdo txd output delay after of txclkout 0.5 4.5 ns t txfpo txframe_pulse outp ut delay after of txclkout 0.5 4.5 ns t parouto sonettx_parout output delay after of txclkout 0.5 4.5 ns t txfppw txframe_pulse width 6 55 ns f rs [21] rxclk frequency f rs nominal (f rs n) can be 155.52 mhz, 77.76 mhz, 38.88 mhz, 19.44 mhz; depends on the bus width and line rate used. f rsn * (1 ? 0.65%) f rsn * (1 + 0.65%) mhz t rxclkp [21] rxclk period 1/(f rs max.) 1/(f rs min.) ns t rxclkod [21] rxclk duty cycle 43 57 % t rxclkr [22] rxclk rise time ? 1.5 ns notes: 21. the parameter is guaranteed by design and is not tested during production. 22. the parameter is guaranteed by charac terization and is not tested during production.
confidential cy7c9536b document #: 38-02078 rev. *g page 33 of 46 t rxclkf [22] rxclk fall time ? 1.5 ns t rxds recovered data set-up to of rxclk 1.5 ? ns t rxdh recovered data hold from of rxclk 1.25 ? ns t rxfps rxframe_pulse set-up to of rxclk 1.5 ? ns t rxfph rxframe_pulse hold from of rxclk 1.25 ? ns t parins sonetrx_parin set-up to of rxclk 1.5 ? ns t parinh sonetrx_parin hold from of rxclk 1.25 ? ns table 7. line interface timing parameter values (continued) parameter description min. max. unit table 8. oif-spi level 3 transmit syst em interface timing parameter values parameter description min. max. unit f tfclk [21] tfclk frequency 104 mhz t tfclkd [21] tfclk duty cycle 40 60 % t tenbs tenb set-up time to tfclk [23] 2?ns t tenbh tenb hold time to tfclk [24] 0.5 ? ns t tdats tdat[31:0] set-up time to tfclk [23] 2?ns t tdath tdat[31:0] hold time to tfclk [24] 0.5 ? ns t tprtys tprty set-up time to tfclk [23] 2?ns t tprtyh tprty hold time to tfclk [24] 0.5 ? ns t tsops tsop set-up time to tfclk [23] 2?ns t tsoph tsop hold time to tfclk [24] 0.5 ? ns t teops teop set-up time to tfclk [23] 2?ns t teoph teop hold time to tfclk [24] 0.5 ? ns t terrs terr set-up time to tfclk [23] 2?ns t terrh terr hold time to tfclk [24] 0.5 ? ns t tsxs tsx set-up time to tfclk [23] 2?ns t tsxh tsx hold time to tfclk [24] 0.5 ? ns t tmods tmod set-up time to tfclk [23] 2?ns t tmodh tmod hold time to tfclk [24] 0.5 ? ns t ptadrs ptadr set-up time to tfclk [23] 2?ns t ptadrh ptadr hold time to tfclk [24] 0.5 ? ns t dtpao tfclk high to dtpa valid [25, 26] 1.5 6 ns t stpao tfclk high to stpa valid [25, 26] 1.5 6 ns t ptcao tfclk high to ptca valid [25, 26] 1.5 6 ns table 9. oif-spi level 3 receive system interface timing parameter values parameter description min. max. unit f rfclk [21] rfclk frequency ? 104 mhz t rfclkd [21] rfclk duty cycle 40 60 % t renbs renb set-up time to rfclk [23] 2?ns t renbh renb hold time to rfclk [24] 0.5 ? ns t rdatd rfclk high to rdat[31:0] valid [25, 26] 1.5 6 ns t rprtyd rfclk high to rprty valid [25, 26] 1.5 6 ns notes: 23. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4v point of the input to the 1.4v point of the clock. 24. when a hold time is specified between an input and a clock, the hold time is the time in the nanoseconds from the 1.4v point of the clock to the 1.4v point of the input. 25. output propagation delay time is the in nanoseconds from the 1. 4v point of the reference signal to the 1.4v point of the out put. 26. maximum output propagation delays are measured with 30-pf load on the inputs.
confidential cy7c9536b document #: 38-02078 rev. *g page 34 of 46 t rsopd rfclk high to rsop valid [25, 26] 1.5 6 ns t reopd rfclk high to reop valid [25, 26] 1.5 6 ns t rerrd rfclk high to rerr valid [25, 26] 1.2 6 ns t rmodd rfclk high to rmod[1:0] valid [25, 26] 1.5 6 ns t rsxd rfclk high to rsx valid [25, 26] 1.5 6 ns table 10.utopia level 3 receive system interface timing parameter values parameter description min. max. unit f rxclk [21] rxclk frequency ? 104 mhz t rxclkd [21] rxclk duty cycle 40 60 % t rxenbs rxenb set-up time to rxclk 2 ? ns t rxenbh rxenb hold time to rxclk 0.5 ? ns t rxdatao rxclk high to rxdata [31:0] valid ? 6 ns t rxsoco rxclk high to rxsoc valid ? 6 ns t rxprtyo rxclk high to rxprty valid ? 6 ns t pxclavo rxclk high to rxclav valid ? 6 ns table 11.utopia level 3 transmit system interface timing parameter values parameter description min. max. unit f txclk [21] txclk frequency ? 104 mhz t txclkd [21] txclk duty cycle 40 60 % t txenbs txenb set-up time to txclk 2 ? ns t txenbh txenb hold time to txclk 0.5 ? ns t txaddrs txaddr set-up time to txclk 2 ? ns t txxaddrh txaddr hold time to txclk 0.5 ? ns t txdatas txdata [31:0] set-up time to tfclk 2 ? ns t txdatah txdata [31:0] hold time to tfclk 0.5 ? ns t txprtys txprty set-up time to tfclk 2 ? ns t txprtyh txprty hold time to tfclk 0.5 ? ns t txsocs txsoc set-up time to tfclk 2 ? ns t txsoch txsoc hold time to tfclk 0.5 ? ns t ptcao tfclk high to ptca valid ? 6 ns table 12.hbst transmit system interface timing parameter values parameter description min. max. unit f tclk [21] tclk frequency 104 mhz t tclkd [21] tclk duty cycle 40 60 % t taddrs taddr[3:0] set-up time to tclk 2 ? ns t taddrh taddr[3:0] hold time to tclk 0.5 ? ns t tdatas tdata [31:0] set-up time to tclk 2 ? ns t tdatah tdata [31:0] hold time to tclk 0.5 ? ns t tparitys tparity set-up time to tclk 2 ? ns t tparityh tparity hold time to tclk 0.5 ? ns t tbvals tbval[2:0] set-up time to tclk 2 ? ns t tbvalh tbval[2:0] hold time to tclk 0.5 ? ns t tdvals tdval_n set-up time to tclk 2 ? ns table 9. oif-spi level 3 receive system interface timing parameter values (continued) parameter description min. max. unit
confidential cy7c9536b document #: 38-02078 rev. *g page 35 of 46 t tdvalh tdval_n hold time to tclk 0.5 ? ns t tsops tsop set-up time to tclk 2 ? ns t tsoph tsop hold time to tclk 0.5 ? ns t teops teop set-up time to tclk 2 ? ns t teoph teop hold time to tclk 0.5 ? ns t terrs terr set-up time to tclk 2 ? ns t terrh terr hold time to tclk 0.5 ? ns t tstfao tclk high to tstfa valid 1.5 6 ns t tsofsto tclk high to tsofst valid 1.5 6 ns t tfasto tclk high to tfast[3:0] valid 1.5 6 ns table 13.hbst receive system interface timing parameter values parameter description min. max. unit f rclk [21] rclk frequency ? 104 mhz t rclkd [21] rclk duty cycle 40 60 % t rreadys rready_n set-up time to rclk 2 ? ns t rreadyd rready_n hold time to rclk 0.5 ? ns t rdatao rclk high to rdata[31:0] valid 1.5 6 ns t raddro rclk high to raddr[7:0] valid 1.5 6 ns t rparityo rclk high to rparity valid 1.5 6 ns t rsopo rclk high to rsop valid 1.5 6 ns t reopo rclk high to reop valid 1.5 6 ns t rerro rclk high to rerr valid 1.2 6 ns t rbvalo rclk high to rbval[2:0] valid 1.5 6 ns t rdvalo rclk high to rdval valid 1.5 6 ns t rstfao rclk high to rstfa valid 1.5 6 ns table 14.memory interface timing parameter description min. max. unit t cyc [21] clkout cycle time 7.5 ? ns t clkouto [22] clkout output de lay after sysclk ? 5 ns t ch [21] clkout high 2.2 ? ns t cl [21] clkout low 2.2 ? ns t co dq output valid after clkout rise ? 5.5 ns t doh dq output hold after clkout rise 0.9 ? ns t ado address output delay after clkout rise ? 5.5 ns t adoh address output hold after clkout rise 0.9 ? ns t ceno cen output delay after clkout rise ? 5.5 ns t cenoh cen output hold after clkout rise 0.9 ? ns t weo we output delay after clkout rise ? 5.5 ns t weoh we output hold after clkout rise 0.9 ? ns t advo adv/ld output delay after clkout rise ? 5.5 ns t advoh adv/ld output hold after clkout rise 0.9 ? ns t ds dq input set-up before clkout rise 2.8 ? ns t dh dq input hold after clkout rise 0.5 ? ns table 12.hbst transmit system interface timing parameter values (continued) parameter description min. max. unit
confidential cy7c9536b document #: 38-02078 rev. *g page 36 of 46 table 15.cpu system interface timing parameter values parameter description min. max. unit f sysclk [21] sysclk frequency 133 133.33 [27] mhz t sysclkd [21] sysclk duty cycle 45 55 % f cpuclk [21] cpuclk freq. ? 66 mhz t cpuadss cpuads_n set-up time to cpuclk 7 ? ns t cpuadsh cpuads_n hold time to cpuclk 2 ? ns t cpuads cpuad set-up time to cpuclk 7 ? ns t cpuadh cpuad hold time to cpuclk 2 ? ns t cpuadz [21] cpuad float ? 14 ns t cpuado cpuad output delay after cpuclk rise ? 10.1 t cpuwrrds cpuwrrd set-up time to cpuclk 7 ? ns t cpuwrrdh cpuwrrd hold time to cpuclk 2 ? ns t cputao cputa_n valid delay ? 10.1 ns t cpublasts cpublast_n set-up to cpuclk 7 ? ns t cpublasth cpublast_n hold to cpuclk 2 ? ns t cpusels cpusel set-up to cpuclk 7 ? ns t cpuselh cpusel hold to cpuclk 2 ? ns t cpuinto cpuint valid delay ? 10.1 ns table 16.toh serial interface receive timing parameter values parameter description min. max. unit t clk2mhzh [21] clk2mhz high period 31 34 sysclk cycles t clk2mhzl [21] clk2mhz low period 31 34 sysclk cycles t clk2mhzr [22] clk2mhz rise time ? 6 ns t clk2mhzf [22] clk2mhz fall time ? 6 ns t repw [22] re1strobe or re2strobe pulse width 62 67 sysclk cycles t reo re1strobe or re2strobe output delay after clk2mhz rising edge ?8ns t tohsdouto tohsdout output delay after clk2mhz rising edge ? 8 ns table 17.poh serial interface receive timing parameter values parameter description min. max. unit t clk16mhzh [21] clk16mhz high period 3 5 sysclk cycles t clk16mhzl [21] clk16mhz low period 3 5 sysclk cycles t clk16mhzr [22] clk16mhz rise time ? 6 ns t clk16mhzf [22] clk16mhz fall time ? 6 ns t rpohpw [22] rpohstart pulse width 7 9 sysclk cycles t rpoho rpohstart output delay after clk16mhz rising edge ? 8 ns t pohsdouto pohsdout output delay afte r clk16mhz rising edge ? 8 ns
confidential cy7c9536b document #: 38-02078 rev. *g page 37 of 46 note: 27. all vc mode configurations require a sysclk frequency of 133.33 mhz. table 18.toh serial interface transmit timing parameter values parameter description min. max. unit t clk2mhzh [21] clk2mhz high period 31 34 sysclk cycles t clk2mhzl [21] clk2mhz low period 31 34 sysclk cycles t clk2mhzr [22] clk2mhz rise time ? 6 ns t clk2mhzf [22] clk2mhz fall time ? 6 ns t tepw [22] te1strobe or te2strobe pulse width 62 67 sysclk cycles t teo te1strobe or te2strobe output delay after clk2mhz rising edge ?8ns t tohsdins set-up time of tohsdin before the falling edge of clk2 mhz 50 ? ns t tohsdinh hold time of tohsdin after the falling edge of clk2 mhz 50 ? ns table 19.poh serial interface transmit timing parameter description min. max. unit t clk16mhzh [21] clk16mhz high period 3 5 sysclk cycles t clk16mhzl [21] clk16mhz low period 3 5 sysclk cycles t clk16mhzr [22] clk16mhz rise time ? 6 ns t clk16mhzf [22] clk16mhz fall time ? 6 ns t tpohpw [22] tpohstart pulse width 7 9 sysclk cycles t tpoho tpohstart output delay after rising edge of clk16mhz ? 8 ns t pohsdins set-up time of pohsdin before falling edge of clk16mhz 20 ? ns t pohsdinh hold time of pohsdin after falling edge of clk16mhz 20 ? ns
confidential cy7c9536b document #: 38-02078 rev. *g page 38 of 46 switching waveforms line transmit and receive interface timing t rxds t rxdh t rxclkh t rxclkl t rxclkp rxclk rxd[31:0] t txdo txclkout txd[31:0] rxfps t rxframe_pulse t rxfph parins t sonetrx_parin t parinh txframe_pulse sonettx_parout t txfpo t txfppw t parouto t txclkip txclki t txclkr t txclkf t txclkp
confidential cy7c9536b document #: 38-02078 rev. *g page 39 of 46 transmit oif-spi level 3 system interface timing switching waveforms (continued) tfclk tenb tdat[31:0] tprty tsop teop terr dtpa[3:0] t tenbs tsx ptadr[3:0] tmod[1:0] stpa ptca t tenbh t tdats t tdath t tprtys t tprtyh t tsops t tsoph t teops t teoph t terrs t terrh t tsxs t tsxh t ptadrs t ptadrh t tmods t tmodh t dtpao t stpao t ptcao
confidential cy7c9536b document #: 38-02078 rev. *g page 40 of 46 receive oif-spi level 3 system interface timing transmit utopia level 3 system interface timing switching waveforms (continued) rfclk renb rdat[31:0] rprty rsop reop rerr rval t renbs t renbh t rdato t rprtyo t rsopo rmod[1:0] rsx t reopo t rerro t rvalo t rmodo t rsxo txclk txenb txaddr[4:0] txdata[31:0] txprty txsoc ptca t txenbs t txenbh t txaddrs t txaddrh t txdatas t txdatah t txprtys t txprtysh t txsocs t txsoch t ptcao
confidential cy7c9536b document #: 38-02078 rev. *g page 41 of 46 receive utopia level 3 system interface timing transmit hbst system interface timing switching waveforms (continued) rxclk rxenb rxdata[31:0] rxprty rxsoc rxclav t rxenbs t rxenbh t rxdatao t rxprtyo t rxsoco t rxclavo tclk taddr[3:0] t taddrs tdata[31:0] tbval[1:0] tdval_n tsop teop terr tparity tstfa tsofst tfast[3:0] t taddrh t tdatas t tdatah t tbvals t tbvalh t tdvals t tdvalh t tsops t tsoph t teops t teoph t terrs t terrh t tparitys t tparityh t tstfao t tsofsto t tfasto
confidential cy7c9536b document #: 38-02078 rev. *g page 42 of 46 receive hbst system interface timing memory interface timing switching waveforms (continued) rclk rready_n t rreadys rerr rstfa rparity raddr[7:0] rdata[31:0] rbval[1:0] rdval rsop reop t rreadyh t raddro t rdatao t rbvalo t rdvalo t rsopo t reopo t rerro t rstfao t rparityo t ch clkout t cl t cyc cen t cenoh t ceno t adoh t ado ad[18:0] dq1[31:0] & dq2[31:0] t clz t co t doh t ds t dh data in data out t chz t weoh t weo we t advo adv/ld sysclk t advoh t clkouto
confidential cy7c9536b document #: 38-02078 rev. *g page 43 of 46 cpu system interface timing switching waveforms (continued) cpuclk cputs_n / cpuads_n cpuad[31:0] cpuwrrd cputa_n cpublast_n / cpubdip_n t cpuadss t cpuadsh t cpuads t cpuadh t cpuadz t cpuwrrds t cpuwrrdh t cputao t cpublasth t cpublasts (input) cpuad[31:0] (output) t cpuado t cpusels t cpuselh chipsel cpuint t cpuinto
confidential cy7c9536b document #: 38-02078 rev. *g page 44 of 46 toh serial interface timing poh serial interface timing switching waveforms (continued) clk2mhz t clk2mhzp t clk2mhzr t clk2mhzf re1strobe re2 strobe t tohsdouto t reo t reo t repw te1strobe te2 strobe t teo t teo t tepw tohsdout tohsdin t tohdins t tohdinh clk16mhz t clk16mhzp t clk16mhzr rpohstart t rpoho t rpoho t rpohsdouto t rpohpw tpohstart t tpoho t tpoho t tpohpw pohsdout pohsdin t pohsdins t pohsdinh t clk16mhzf
confidential cy7c9536b document #: 38-02078 rev. *g page 45 of 46 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. ordering information package diagram please see device manual and errata document for further deta ils on functional descriptions. posic2gvc and nobl are trade- marks of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. speed ordering code package name package type operating range standard CY7C9536B-BLC 504l2bga 504-pin bga commercial standard cy7c9536b-bli 504l2bga 504-pin bga industrial 504-lead l2 ball grid array (37.50 x 37.50 x 1.57 mm) bl504 51-85147-*c
confidential cy7c9536b document #: 38-02078 rev. *g page 46 of 46 document history page document title:cy7c9536b oc-48/stm-16 framer with vc - posic2gvc? document number: 38-02078 rev. ecn no. issue date orig. of change description of change ** 127207 07/03/03 qjl new data sheet *a 129314 10/17/03 cfk clarified phy connection in posic2gvc logic block diagram added specification references section changed note 18 to include stsx-1v added single posic2gvc aps implementation scheme description removed statement that pi n assignment is tentative added 16-bit mode operation pin description for tmod and rmod clarified that posic_oen signal tri-states all posic2gvc outputs added that scan_ena should be pulled low for normal operation changed clk_out to clkout in pin assignment table added parameters pw (total chip power) and ios (output short circuit current) to dc specifications changed compatible nobl part number to cy7c1370b/c corrected notes for parameters guaranteed by design/char changed trerrd/trerro parameter minimum from 1.5 ns to 1.2 ns changed tdoh, tadoh, tcenoh, tweoh, ta dvoh from min 0.5 ns to min 0.9 ns changed fsysclk to max 133.33 mhz updated package name in ordering information table removed errata sect ion (reference separa te errata document) changed posic2gvcb to posic2gvc. *b 130893 12/24/03 cfk added note to table 1 (vc bandwidth) and table 15 (sysclk timing parameter) to indicate that all vc mode channel configurations require a sysclk frequency of 133.33 mhz changed data sheet to final status *c 132897 01/26/04 cfk no document change. publish first page to web. *d 207426 see ecn cfk removed statement that pinout is tentative in pin assignment section updated table 6 compatible nobl sram part numbers removed sdl and hdl spec references throughout document changed generic protocol encapsulator references through document to gfp encapsulator *e 215296 see ecn pir no content c hange. post to web under nda. *f 318033 see ecn qjl updated icc3 from 0.26 to 0.75. updated icc5 from 0.1 to 0.28. updated icc1 from 2 to 1. updated power from 4.57 to 4.58. post web under nda. *g 355154 see ecn qjl changed pin description for oe to note tie to vss2.

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